PCI buses have been in common use to serve as system buses that give connection between devices in personnel computers (PC), various types of electronic equipment, or the like. Such system buses are employed in order to build a system architecture that does not depend on a higher data transfer rate or a high-performance processor.
A PCI bus carries out every data transfer in a principle of block transfer, which is realized in a process of burst transfer. This allows the PCI bus to yield a maximum data transfer rate of 133 megabyte per second (MBps) (when the bus has a data transfer capacity of 32 bits). The PCI bus is specified to support both memories and I/O address spaces for burst transfer.
When a system includes a processor or a bus master that creates data bursts in an I/O address space, I/O data bursts created by the processor or bus master enable even faster data transfer between I/O devices and between system memories and the I/O devices, which leads to improved system performance.
As a conventional technique to offer faster data transfer, such a computer system is suggested (for example, see Japanese Patent No. 3579149) that is devised in a try to increase the speed of a process of access to a known I/O-mapped I/O device, the process being executed by a CPU or a bus master other than the CPU via a PCI bus.
The computer system disclosed in Japanese Patent No. 3579149 includes a means for designating I/O devices, which are assigned to a given I/O address on a PCI bus, as a memory space and generating a memory cycle in response to a request for I/O access to the I/O devices, and a means for turning the memory cycle into a series of I/O cycles for access to the I/O devices.
The system described in Japanese Patent No. 3579149 allows a CPU to function as a bus master and provide access to the I/O devices, but is incapable of showing sufficient bus performance in access to a high-speed I/O device because of the memory cycle generated in response to the I/O access request. Specifically, according to the system described in Japanese Patent No. 3579149, data access to the I/O devices and to memories are switched via a bridge circuit, and the CPU does not have to interfere at least with data transfer in memory access but has to interfere with every data transfer involving burst transfer. This makes it impossible for the system to carry out data transfer to the high-speed I/O device under sufficient bus performance.
The technique according to the system described in Japanese Patent No. 3579149 is characterized by the CPU working as a bus master to provide access to a specific I/O device, which may be an HDD. The HDD is controlled by an HDD controller, which works as a bus master to control data transfer involving access to the HDD. In this data transfer process, bus performance becomes insufficient when a targeted PCI device other than the HDD controller in the data transfer is a device performing slowly in slave access (target access).
For example, such a case can be assumed that the HDD controller is connected to a PCI device A other than the HDD, the device A being slow in target access, via a bus. When the PCI device A is a data transfer target and the HDD controller makes access to the PCI device A slow in target access, a process to be carried out is the one as shown in the left-half of a timing chart (e.g. transfer of 8 bursts of data) exhibited in FIG. 3. The chart demonstrates that the PCI device A, slow to process target access, causes the HDD controller to wait by sending out a TRDY signal from a PCI hF (Interface) on the PCI device A. In this case, therefore, an efficient transfer process is not executed.
The above case applies not only to the technique according to the Japanese Patent No. 3579149, but also to techniques in popular use. In many cases, due to features in system designing the system can include specific combination of circuits, another PCI device connected to an HDD controller that can be a device slow in slave access, or an HDD controller may be connected to an IC (Integrated Circuit) chip having a PCI device slow in slave access.
One reason for slow data transfer in a slave access process is that, for a certain type of PCI device, a PCI device carries out such a process that it stops a PCI bus immediately after receiving data from the PCI device to write the data into a local memory, and asks for data on the PCI bus again after finishing writing. Meanwhile, the PCI bus works on faster data transfer through a burst transfer process of sending out an address first and data in succession. Upon receiving data, the PCI bus brings together, for example, 32 bursts of data for burst transfer to increase process speed, for example, in writing the data into a page memory. In speeding up data transfer, an improvement in repeated stoppage of and data request to the PCI bus may be one approach to take, but, in principle, PCI bus controllers are not designed for high-speed performance, which makes such improvement difficult to achieve.